This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-398388, filed on Dec. 27, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a level shifter for converting an input voltage level to a desired voltage level and outputting it and a semiconductor memory device having the level shifter and, in particular, a nonvolatile semiconductor memory device having the level shifter.
2. Description of the Related Art
Conventionally, a flash memory has been known as one of a nonvolatile semiconductor memory device. This flash memory is comprised of an EEPROM (electrically erasable PROM) and can erase data, at a time, stored in memory cells belonging to a block.
Now an explanation will be made below about a conventional flash memory.
FIG. 1 is a cross-sectional view showing a memory cell of a conventional flash memory.
An n type well area 102 is formed in a p type silicon semiconductor substrate 101 and a p type well area 103 is formed in the n type well area 102. In the p type well area 103, a drain diffusion region (n+type region) 104 and a source diffusion region (n+type region) 105 are formed such that they are spaced by a predetermined distance from each other.
A floating gate 107 is formed over the p type well region 103 between the drain diffusion region 104 and the source diffusion region 105 with a gate insulating film 106 interposed. Further, a control gate 109 is formed over the floating gate 107 with an insulating film 108 interposed.
In the so constructed memory cell, a threshold voltage as seen from the control gate 109 varies by the number of electrons stored in the floating gate 107.
FIG. 2 is a circuit diagram showing a configuration of a memory cell array comprised of a matrix array of such memory cells.
The control gate 109 of the memory cell MC is connected to a corresponding one of word lines WL0 to WLn. The drain of the memory cell MC is connected to a corresponding one of bit lines BL0 to BLm. The source of the memory cell MC is connected to a ground potential Vs.
FIG. 3 is a graph showing a drain current in the memory cell transistor. In the graph, data xe2x80x9c0xe2x80x9d represents a state corresponding to a relatively large number of electrons stored in the floating gate 107, that is, a high state of a threshold voltage Vt. On the other hand, data xe2x80x9c1xe2x80x9d represents a state corresponding to a relatively small number of electrons stored, that is, a low state of the threshold voltage Vt.
FIG. 4 shows the biasing conditions of data read, data write and data erase operations. In the data read operation, a gate voltage Vg is set to be 5V and a drain voltage Vd is set to be 1V. The data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is decided depending upon whether or not there is a flowing of a cell current. The data erase operation is performed on each plurality of memory cells, at a time, sharing the source diffusion region 105 and p well area 103. In the data erase operation, the gate voltage is set to be xe2x88x927.5V and the source voltage Vs is set to be 9V. In the data erase operation, electrons flow from the floating gate 107 into the substrate (p type well area 103) due to the F-N tunneling phenomenon and those erase target""s memory cells are set to all xe2x80x9c1xe2x80x9d.
Further, the Data write operation is performed at each bit unit. By biasing, to 5V, a bit line (Vd) on the cell to which the data xe2x80x9c0xe2x80x9d is written, the electrons of high energy generated due to a xe2x80x9cchannel hot electron phenomenonxe2x80x9d are injected into the floating gate 107. The bit line of a cell on which the data xe2x80x9c1xe2x80x9d is to be held to the data xe2x80x9c1xe2x80x9d is set to 0V. At this time, there occurs no injection of the electrons and there is no variation in the threshold voltage.
In order to confirm whether, or not the write and erase operations are correctly performed, a write- and an erase-verifying operation are performed. The write-verifying operation is performed by reading out xe2x80x9c0xe2x80x9d under the application of a higher voltage Vpv than a voltage Vread at a reading time to the gate (see FIG. 3). The write operation and the write-verifying operation are alternately performed and, when those write target""s cells are set to all xe2x80x9c0xe2x80x9d, the write operation is completed.
At the erase operation, the erase-verifying operation is performed by reading unit xe2x80x9c1xe2x80x9d under the application of a lower voltage Vev than the voltage Vread at the reading time to the gate and, by doing so, a cell current Icell is adequately secured. As evident from the above, the word line voltage (gate voltage) on the memory cell varies in a various way.
Therefore, use is made of a level shifter for switching the word line voltage of the memory cell to above a power supply voltage or a negative voltage.
FIG. 5A shows a circuit diagram showing an arrangement of a conventional level shifter.
A high level shifter 101 is a circuit for converting a high-side voltage Vcc of an input signal IN and comprises n channel MOS transistors (hereinafter referred to as nMOS transistors) N21, N22 and p channel MOS transistors (hereinafter referred to as pMOS transistors). A low level shifter 102 is a circuit for converting a low-side voltage Vss (0V) of the input signal IN and comprises nMOS transistors N23, N24, N25 and N26 and pMOS transistors P23 and P24.
The operation of the level shifter will be explained below with the use of FIG. 5B.
FIG. 5B is a timing chart showing the operation of the level shifter. When the input signal IN is at a xe2x80x9c0Vxe2x80x9d, a node MID is set to 0V and a node MIDB is set to a voltage Vsw. And an output signal OUT appears as a voltage Vbb.
When, after this, the input signal IN varies from a xe2x80x9c0Vxe2x80x9d to a voltage Vcc the node MID varies from the xe2x80x9c0Vxe2x80x9d to a voltage Vsw and the node MIDB varies from the voltage Vsw to the xe2x80x9c0Vxe2x80x9d. And the output signal OUT varies from the voltage Vbb to the voltage Vsw.
Incidentally, as in other memory devices, the flash memory has also been formed as a high density integration unit with the microminiaturization of the memory cell. A transistor for high voltage is used for a row decoder and column gates, but such transistors needs to be laid out at a pitch of the memory cells and the scaling (downsizing) of the transistors is important to their high density integration. By converting a high voltage necessary to the writing and erasing of data to and from the memory cells, it is possible to achieve the scaling (downsizing) of the transistors for high voltage.
If, however, the high voltage necessary to the writing and erasing of the data to and from the memory cells is converted to a low voltage, the circuit operation of the level shifter shown in FIG. 5A becomes difficult. In the level shifter, a high level shifter 101 and low level shifter 102 can be adequately operated under the conventional voltage conditions of Vsw=2.5V and Vbb=xe2x88x927.5V at a data erasing time. At this time, a maximum voltage of 10V is applied between the gate and the source, or between the source and the drain, of the transistor. If the maximum voltage is, for example, 9V for the downsizing of the transistor for high voltage, when the voltage on the word line is a constant voltage of xe2x88x927.5V, the voltage conditions at the data erasing time will be Vsw=1.5V and Vbb=xe2x88x927.5V. If, at this time, Vsw=1.5V, it becomes difficult to invert the output of the level shifter because the ON resistance of the pMOS transistor is large.
A level shifter according to an aspect of the present invention comprises a latch circuit having a first node and a second node set to a first voltage or a second voltage, the second node being set to the second voltage when the first node is set to the first voltage and the second node being set to the first voltage when the first node is set to the second voltage; a first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor being connected to the first node, a first signal being supplied to the second terminal of the first capacitor; and a second capacitor having a third terminal and a fourth terminal, the third terminal of the second capacitor being connected to the second node, when the first signal is supplied to the second terminal of the first capacitor, an inverted replica of the first signal being supplied to the fourth terminal of the second capacitor.